1. Field of the Invention
The present invention relates to a method and an apparatus for forming a layout pattern of a semiconductor integrated circuit, more particularly, to a method and an apparatus for forming a layout pattern of a semiconductor integrated circuit using a cell generator which automatically forms a layout pattern of a large scale integrated circuit (LSI) to simplify processing and carry out high speed operation of the cell generator using layout information of an existing layout pattern.
2. Description of the Related Art
Recently, a CAD (computer aided design) tool such as a cell generator for automatically forming a hard mask of a gate array or a mask pattern in a cell library of a standard cell LSI has been studied and improved. Furthermore a method for forming a layout pattern of a semiconductor integrated circuit using the cell generator, is actively being studied. In the automatic forming processes of a layout pattern, automatic layout techniques and automatic wiring techniques in a cell or a functional block have become advanced, and are now actually being used.
Generally, a functional block, such as a cell in a cell library of a standard cell LSI, is formed by a cell generator using logical information, and the logical information, which includes connection information and layout information, is indicated by a logical circuit diagram or a programming language, i.e., a logical description language. Note, for example, information of a logical circuit diagram is processed in a CAD tool, that is, a logical circuit diagram is entered into the CAD tool and data of the logical circuit diagram is translated into a logical description language. A layout pattern of the functional block is, for example, formed by the cell generator by inputting logical information of a logical description language. Note, the logical information of the logical description language may be directly produced or input by a human operator.
As described above, a layout pattern is automatically formed by carrying out the placement process and the routing process of the transistor-constitution level. Note, the layout pattern obtained by the cell generator is not only one type but a plurality of types, and it is difficult to obtain an optimum layout pattern from those plural layout patterns. Further, almost all layout patterns formed by the cell generator are larger size than a layout pattern formed by a person. Consequently, in practice, placement processing of small blocks is previously carried out by a person, and only the routing process is carried out by a computer system, e.g., a cell generator.